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Built-in self-test (BIST), once reserved for complex digital chips, can now be found in devices with relatively small amounts of digital content. The move to fine-line process geometries has enabled data converters to include BIST functionality. This allows hierarchical test strategies to be implemented, providing a powerful feature for enhancing system reliability.
The entire system-clock signal chain must be understood in order to achieve optimal performance from an A/D converter. It can be discouraging to find that a circuit's accuracy is clock-jitter limited, as this problem could have been prevented during the design phase. Decreased clock jitter can be achieved through frequency division, filtering, use of an improved clock source, and proper choice of auxiliary hardware.