Tuesday, February 05, 2008

Analog/Digital-Converter Clock Optimization: A Test Engineering Perspective

The entire system-clock signal chain must be understood in order to achieve optimal performance from an A/D converter. It can be discouraging to find that a circuit's accuracy is clock-jitter limited, as this problem could have been prevented during the design phase. Decreased clock jitter can be achieved through frequency division, filtering, use of an improved clock source, and proper choice of auxiliary hardware.


Post a Comment

<< Home